The present invention relates to a video processing scheme, and more particularly, to a method and related apparatus for generating interpolated frames according to input frame source.
Frame rate conversion from a lower rate to a higher rate can be achieved by frame repeating or motion compensated interpolation such as motion judder cancellation (MJC). Frame rate conversion is required when a frame rate associated with source frames is different from the display frame rate of a display device. In general, there are several common source frame rates, such as 50/60 frames per second (i.e., 50/60 Hz) for video source, or 50 Hz with 25 frames per second or 60 Hz with 24/30 frames per second for film source. For example, video frames with 50 Hz frame rate are adopted in the PAL system (European standard) while video frames with 60 Hz frame rate are used in the NTSC system (US standard). In contrast, film frames are usually captured with a rate (e.g. 24/25/30 Hz) that is much lower than the video frames (e.g. 50/60 Hz). Consequently, some frames of the film frames are repeated to produce a sequence of frames with a rate of 50/60 Hz.
For example, for a DVD player in Taiwan, a transmission frame rate is 60 Hz in common. If source film frames are originally captured at 24/30 frames per second, image data received by the DVD player will include repeated image content. In particular, the image data is called a 2:2 sequence if the source film frames are captured at 30 Hz initially; otherwise, the image data is called a 3:2 sequence if the source film frames are captured at 24 Hz. In order to display the image on a display device in a smooth manner, repeated frames in the source film frames are replaced by one or more interpolated frames. FIG. 1 shows a table illustrating various interpolation methods that can be used for displaying source frames having different frame rates at different display frame rates. In the first case, since the input source frame rate 50/60 Hz is identical to the display frame rate 50/60 Hz, frame interpolation is not needed. In the second case, in order to display video frames having a frame rate 50/60 Hz at a display frame rate 100/120 Hz, video mode interpolation is required for achieving double frame rate interpolation. That is, one interpolated frame is inserted between every two adjacent video frames. In the third case, although the film frames have a transmission frame rate identical to the display frame rate (both are 50/60 Hz), a film mode interpolation is used for replacing repeated frames by interpolated frames, where the repeated frames are originally applied to increasing a frame rate of the film frames from the capture frame rate 24/25/30 Hz to the transmission frame rate 50/60 Hz. The fourth case applies the film mode interpolation, so the repeated frames are replaced by more than one interpolated frames. For example, if film frames having a capture frame rate of 30 frames per second are displayed at a display frame rate of 120 Hz, three out of every four frames are generated by interpolation while only one frame is an original source film frame.
FIG. 2 is a diagram illustrating a conventional motion compensated interpolation device 200 and a timing diagram of operation of the interpolation device 200. As shown in the top half of FIG. 2, the device 200 includes a processing circuit 205 and a memory 210, where incoming frames are first written into the memory 210 and then the processing circuit 205 analyzes motion vectors associated with the incoming frames stored in the memory 210 to generate interpolated frames. Thus, the memory 210 needs to allocate part of bandwidth to a write data channel W0 in FIG. 2 for receiving the incoming frames. Simultaneously, the processing circuit 205 also reads data stored in the memory 210 to analyze the incoming frames, e.g., the processing circuit 205 may read data of two frames from the memory 210 each time to generate an interpolated frame for achieving double frame rate conversion. Therefore, in this situation, the memory 210 also allocates part of bandwidth to read data channels R1 and R2 in FIG. 2 for transmitting data to the processing circuit 205. Moreover, another read data channel R3 will also occupy part of bandwidth of the memory 210 due to film mode detection.
Referring to the bottom half of FIG. 2, it is assumed that the incoming frames are comprised by video frames A0, B0, F0, G0, and film frames C0, C1, D0, D1, E0, E1 (i.e., a 2:2 sequence), where the film frames C1, D1, and E1 are copies of the film frames C0, D0, and E0, respectively. In this example, the device 200 performs double frame rate up-conversion (e.g., converting the transmission frame rate 50 Hz to the display frame rate 100 Hz), and also performs the film mode detection upon the incoming frames for deciding how to produce interpolated frames so as to generate the desired output frames shown in FIG. 2. The frame A0B0 is an interpolated frame inserted between the video frames A0 and B0 while the frames C0D0, C0D0′, and C0D0″ are different interpolated frames inserted between the film frames C0 and D0; other interpolated frames between video/film frames are also processed in a similar manner. Performing the film mode detection is usually to detect whether two adjacent frames are duplicates or not at each time; if two adjacent frames are found to be different, the two adjacent frames are estimated as video frames and then an interpolated frame is directly generated according to these video frames without occupying part of bandwidth of the memory 210 to read another data from the memory 210. For instance, when it is detected that the frame A0 is different from the frame B0, the processing circuit 205 can directly use the frames A0 and B0 to generate the interpolated frame A0B0 without reading other data from the memory 210. However, if it is detected that frames C0 and C1 are duplicates (i.e., the frames C0 and C1 are film frames), the processing circuit 205 needs to read the frame D0 from the memory 210 through the above-mentioned read data channel R3, for generating the interpolated frames C0D0, C0D0′, and C0D0″. In this situation, the bandwidth of the memory 210 is occupied by at least the above-mentioned data channels W0, R1, R2, and R3. Additionally, in another example, if the incoming frames include a 3:2 sequence instead of the 2:2 sequence, two frames for interpolation may be different from two adjacent frames for film mode detection at one time since a original source frame in the 3:2 sequence is followed by one or two repeated frame(s). That is, the processing circuit 205 requires four read data channels. In other words, in order to convert a film input originally captured at 24 or 30 frames per second to a display output with 120 Hz, more bandwidth must be allocated to write frames into and to read frames from the memory 210, and the storage space of the memory 210 also need to be large enough for buffering these incoming frames. However, increasing the bandwidth and storage space of the memory 210 raises production costs.